The present disclosure relates to semiconductor memory devices, and more particularly to a technique for controlling the threshold voltages of reference cells included in semiconductor memory devices.
FIG. 14 illustrates an example configuration of a conventional semiconductor memory device. In the semiconductor memory device, memory cells MC911 and MC921 are coupled to a word line WL91, and memory cells MC912 and MC922 are coupled to a word line WL92. The memory cells MC911 and MC912 are coupled to a sub bit line SBL91, and the memory cells MC921 and MC922 are coupled to a sub bit line SBL 92. A voltage supply VMS9 applies a read voltage to a read target memory cell of the memory cells MC911, MC912, . . . , MC922.
Main bit lines MBL91 and MBL92 correspond to the sub bit lines SBL91 and SBL92, respectively. A decoder DEC9 couples one of the sub bit lines SBL91 and SBL92, which is coupled to the read target memory cell, to the main bit line corresponding to the sub bit line. Reference bit lines RBL91 and RBL92 correspond to the main bit lines MBL91 and MBL92, respectively. A reference cell RC91 corresponds to the memory cells MC911 and MC912, and a reference cell RC92 corresponds to the memory cells MC921 and MC922. The reference cells RC91 and RC92 are coupled to a reference word line RWL91, and coupled to the reference bit lines RBL91 and RBL92 via switches RSL91 and RSL92, respectively. A voltage supply VRS9 applies a read voltage to one of the reference cells RC91 and RC92 corresponding to the read target memory cell. A sense amplifier SA91 is coupled to the main bit line MBL91 and the reference bit line RBL91, and a sense amplifier SA 92 is coupled to the main bit line MBL92 and the reference bit line RBL92.
FIG. 15 illustrates an example configuration of the sense amplifier SA91 shown in FIG. 14. In the sense amplifier SA91, a level shifter LS9 converts a voltage of the main bit line MBL91 and a voltage of the reference bit line RBL91 to voltages within a range of operation of a differential amplifier circuit COM9. The differential amplifier circuit COM9 amplifies a voltage pair from the level shifter LS9 and outputs as output voltages O91 and O92. A latch circuit LAT9 converts voltage levels of the output voltages O91 and O92 to logic levels (voltage levels at which it can be determined whether data is 0 or 1).
When a memory cell MC911 is read, the voltage supply VMS9 applies a read voltage (e.g., a voltage of about 1 V) to the memory cell MC911. The decoder DEC9 couples the sub bit line SBL91 to the main bit line MBL91. A drive voltage (e.g., a voltage of about 4 V) is applied to the word line WL91. Also, the voltage supply VRS9 applies a read voltage (e.g., a voltage of about 1 V) to the reference cell RC91, the switch RSL91 is put in a conduction state. A drive voltage (e.g., a voltage of about 4 V) is applied to the reference word line RWL91.
A bit line parasitic capacitance (CBL) of the main bit line MBL91 is charged with a current generated in the main bit line MBL91 (i.e., a current generated in the read target memory cell MC911). Thus, as shown in an upper graph of FIG. 16, a voltage (VinM) of the main bit line MBL91 gradually rises as time progresses. A voltage (VinR) of the reference bit line RBL91 rises similarly. The amount of rise in the voltage (VinM) of the main bit line MBL91 over time changes depending on magnitude of the threshold voltage of the memory cell MC911 (or MC912).
At the start of the latch operation of the latch circuit LAT9 of the sense amplifier SA91, when the voltage (VinM) of the main bit line MBL91 is higher than the voltage (VinR) of the reference bit line RBL91, the latch circuit LAT9 sets the voltage level of the output voltage O91 to a “1” data level (see the solid line in the lower graph of FIG. 16). On the other hand, when the voltage (VinM) of the main bit line MBL91 is lower than the voltage (VinR) of the reference bit line RBL91, the latch circuit LAT9 sets the voltage level of the output voltage O91 to a “0” data level (see the dashed line in the lower graph of FIG. 16). Note that a voltage waveform Vo91 corresponds to the waveform of the output voltage O91, and a voltage waveform Vo92 corresponds to the waveform of the output voltage O92.
As described above, it is determined whether the voltage level of the output voltage O91 is a “1” data level or a “0” data level in accordance with the magnitude relation between a current value of a reference cell (a voltage value of a reference bit line) and a current value of a memory cell (a voltage value of a main bit line) input to the sense amplifier. Each of the memory cells MC911, MC912, . . . , MC922 defines whether data stored in the memory cell is “1” or “0” in accordance with the threshold voltage of the memory cell. Since a change in a current value (a difference between a current value where data “0” is stored and a current value where data “1” is stored) according to a change in the threshold voltage of the memory cell is small, the threshold voltages of the reference cells RC91 and RC92 need to be accurately set so that current values of the reference cells RC91 and RC92 are equal to a median of a change width of the current value of the memory cell (a median between a current value where data “0” is stored and a current value where data “1” is stored).
When CMOS transistors are used as the reference cells RC91 and RC92, characteristic variations in manufacture reduce yield. Furthermore, when advance circuit design is used for expanding the acceptable range of the characteristic variations, a chip area increases. On the other hand, when nonvolatile memory devices are used as the reference cells RC91 and RC92, characteristic variations of the reference cells in manufacture can be reduced by controlling the threshold voltages of the reference cells in testing. This hardly causes the reduction in the yield and the increase in the chip area, as described above. Moreover, characteristic variations in read circuits such as a sense amplifier can be controlled by a reference cell being a nonvolatile memory device, and thus, an increase in an operation margin and an improvement in a specification are expected.
In general, the threshold voltage of a reference cell is initialized as follows. First, the current value of the reference cell is measured. When the current value of the reference cell does not reach a desired current value, a bias voltage is applied to the reference cell to change the threshold voltage of the reference cell. Until the current value of the reference cell reaches the desired current value, this process is repeated. As such, the threshold voltage of the reference cell is controlled.
While, in recent years, various methods have been suggested for controlling the threshold voltage of a reference cell, higher-speed control is required in view of manufacturing costs. Also, in order to reduce an increase in an area, high-speed control is performed by comparing and determining whether the current value of the reference cell is equal to a desired current value, using a sense amplifier for normal read operation. For example, Japanese Patent Publication No. 2004-39075 and Japanese Patent Publication No. 2006-294135 teach achieving high-speed control using a reference cell other than a reference cell coupled to a reference bit line. Japanese Patent No. 3237610 and Japanese Patent Publication No. H07-153287 teach eliminating an external terminal (an external terminal required for monitoring a current value when controlling a reference cell) by including a current supply within a chip.